module counter(clk_out1,out[7:0]);
input clk_out1;
output [7:0] out;
reg [7:0] out;

always @(posedge clk_out1)
begin
	if(out[7:4]==5 && out[3:0]==9)
		out<=8'b0000_0000;
	else
		if(out[3:0]==9)
		begin	
			out[7:4]<=out[7:0]+1;
			out[3:0]<=0;	
		end
		else
		out[3:0]<=out[3:0]+1;
end

endmodule